Design and development of an integrated circuit (IC) is a complex, time consuming, and expensive process. To aid in these activities, often times a design team will use a field programmable gate array (FPGA), which is a programmable IC that may be used for purposes of testing and prototyping aspects of the IC design. Many FPGA's provide various configurable interfaces such as a high speed input/output (IO) module that may be used to avoid the costly and time-consuming process to perform application specific integrated circuit (ASIC) design and fabrication. The flexibility and versatility of FPGAs provide a very cost effective standard compliance testing apparatus in terms of both protocol and electrical attributes. However, most FPGA's configurable high-speed serial IO module, if not all, are based on a current mode logic (CML) transceiver and are thus incompatible with other electrical signaling modes such as voltage mode logic.
One area of IC development is with regard to designing ICs that incorporate a physical layer based on the Mobile Industry Processor Interface (MIPI) Alliance MIPI M-PHY specification Version 1.00.00—8 Feb. 2011 (MIPI Board Approved 28 Apr. 2011) (hereafter MIPI M-PHY specification), which is becoming widely adopted as the high-speed low power IO standard for serial interfaces within mobile devices. This physical layer, referred to herein as M-PHY, is developed as a stand-alone physical layer, and is intended for use with various higher level protocols.